Xilinx Ise Design Tools Download

ELEC3500 - Xilinx Project Navigator Tutorial.

This tutorial is valid for Xilinx Project Navigator (ISE 14.7), ModelSim SE-64 10.2c , ATLYS board Reference Manual

� Starting Xilinx Project Navigator

� Creating a new project

� Using ISE 14.7

� iMPACT Device Configuration

� Simulating the design

� Simulating the remaining cases

� Downloading to the Spartan III FPGA

� Erasing the FPGA

� Additional information for the TAs

� Files required for projects

� ISE design Flow

Starting Xilinx Project Navigator

To start the Xilinx Project Navigator, click on the Start menu and select:

All Programs => Xilinx Design Tools => ISE Design Suite 14.7 => ISE design Tools => 64-bit Project Navigator

Creating a new project

You will need to create a project for your design which can be done by choosing:

File => New Project�

The following window will open.
Select a project location on your H: drive (ie: H:\Nagui\). Any directories will be built automatically.
Enter a project name (ie: type your name).
Select HDL for the "Top-level source type:"

Click "Next"

Fill in the device information as shown in the figure below. Clicking on the right of the boxes will show you the choices.

Click "Next"

Click "Finish"

You will need to add your HDL and test bench design which can be done by choosing:

Project => Add Source� (My files are located in H:\Elec3500)

Select the following files (hold Ctrl and left-click each file):

updncounter.v
updncounter_tb.v
updncounter.ucf

Then click Open

Click "OK"

For the Tug Of War competition we will be using Modelsim SE-64 10.2c as we did in ELEC2607. Modelsim is used by high tech companies.

The following step is IMPORTANT.

� Edit => Preferences ...

Click �OK�

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Using ISE 14.7

The Project Navigator should look like the figure below:

iMPACT Device Configuration

When creating a new project, JTAG configuration must be selected. This is done once .

On the "Processes" pane in the Project Navigator window, right click on �Generate Programming File� and select properties.

On the �Startup Options� tab, under FPGA start-up clock, choose � JTAG clock� as shown below.

Do not �OK� yet.

On the "Readback Options" pane, check �Create Readback Data Files� and �Create Mask File�. As shown below.

Click "OK" when done.

About the Readback Options.

By default, ISE does not create the necessary supporting files to enable the Verify option during device programming.

It is not necessary to Verify during programming and doing so will slow down the configuration process.

If you want to use the Verify options, it is necessary to generate the appropriate files as indicated above.

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Simulating the design

You will simulate the design from the Project Navigator using ModelSim.
In the "Sources in Project" frame, click on " testfixture ( updncounter_tb.v )"
In the "Processes for Source" frame, under the "ModelSim Simulator" item, double-click "Simulate Behavioral Model"

This will launch the ModelSim simulator to simulate your design. Several windows should open up.

A dialog box will pop up as shown below. Click "No"

Finish_Vsim_NO

The "wave" window displays the simulated waveforms. There are several buttons to change the zoom on the waveforms:

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Simulating the remaining cases

The default testfixture only covers some cases. You will need to add the remaining cases.
You can edit the file in a text editor, or in the Project Navigator text editor.
In the "Sources in Project" frame, double-click on the test bench ( updncounter_tb.v ) to open the Project Navigator text editor.
Make sure you save the changes to your testfixture file after you have changed it.
Close the ModelSim program before running another simulation. You can only have one copy of ModelSim open at a time.
Re-simulate your design to verify that it works correctly.

Downloading to the Spartan III FPGA. (Field Programmable Gate� Array)

You will download the design from the Project Navigator.
In the "Sources in Project" frame, click on " updncounter.v "
In the "Processes for Source" frame, as shown below, go to:

"Implement Design"

"Generate Programming File"

double-click "Configure Device (iMPACT)"

IMPACT

OR You can start the download by running the iMPACT:

Start => All Programs => Xilinx Design Tools => ISE Design Suite 14.7 => ISE Design Tools => 64-bit Tools => iMPACT

Boundary_Scan

Click Next >

Cable_connect

Click Finish

Boundary_scan_content

Click OK

BIT_file_select

Ignore_warning

This screen will show up if you did not setup the iMPACT device as indicated above iMPACT Device Configuration

Do not panic the iMPACT will take care of this error and use the JtagClk .

Do_not_verify

After compiling your circuit, this will launch the iMPACT program to allow you to download your design to the device.
On the "Configure Devices" window, select "Boundary-Scan Mode" and click "Next"
Select "Automatically connect..." and click "Finish." iMPACT will attempt to connect to the FPGA board.
When the boundary-scan chain is complete, click "OK"
An "Assign New Configuration File" window will open. Select " updncounter.bit " make sure you are pointing to your home directory, and click "Open"
Right-click on the chip icon and select "Program"
On the "Program Options" box, do not check "Verify" then click "OK"
iMPACT will now program the Xilinx FPGA.
The default programming for the buttons is shown below:

BTN0 = pbr
BTN1 = not used
BTN2 = pbl
BTN3 = rst

�� Spartan3_board �� Spartan3_board_diagramme

Notes :

If your design was not successful and you want to program the Spartan III FPGA again, close the iMPACT program before re-starting the process in the Project Navigator.
If your simulation was correct, but the lights don't blink (ie: they blink very fast, or are solid), the clock to the FPGA may be set too fast. You can slow down the frequency of the Hewlett Packard Arbitrary Function Generator (ARB). Please note that the BNC cable should be connected to the SYNC out of the ARB.

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Erasing the FPGA

To erase the FPGA turn off the power using the ON/OFF switch of the FPGA board located on the top Left.

Additional information for the TAs

This section contains some additional information that shouldn't be necessary to do the lab, but may be helpful in preparing future labs or debugging students' circuits.

Files required for projects

For ELEC3500, it is generally easier on the students (and the TAs!) to provide a schematic template with the correct port names as well as complete (or partially complete) test fixtures. It cuts down on the amount of tool specific messing around that the students are required to do, as well as greatly reducing the amount of debugging of students' projects by the TAs.
The students can create the project and add these files as sources during project creation as described earlier in the tutorial.
The files required for a project are preferably posted on a public network drive that the students can access.

Verilog File updncounter.v

// updncounter.v - Written by Gord Allan Jan 30/2003 for 350 lab 3.

module updncounter(clk, rst, pbl, pbr, leds_out, status);��

�� // We need to call the main pins in and out of our design the same as they are on the FPGA board

�� input clk;�� // from the clock pin on the function generator

�� input rst;�� // from the center push-button on the FPGA board

�� input pbl;�� // used for our count down control

�� input pbr;�� // used for our count up control

�� output [6:0] leds_out;�� // the lights on the FPGA board

�� output [3:0] status;�� // additional active low LEDS available for troubleshooting

�� // Finally, as in any language, there are some declarations required.

�� wire cntdwn_from_pushbutton;��

�� wire cntup_from_pushbutton;��

�� reg [6:0] counter;

�� reg [6:0] next_count;

�� reg cntdwn;

�� reg cntup;

�� // But, in our design they use different names, and so we must perform the mappings.

�� assign status = 4'b1111;�� // if the extra LEDS are not used turn them off

�� assign cntdwn_from_pushbutton = pbl;�� // map them to the external names

�� assign cntup_from_pushbutton � = pbr;�� // map them to the external names

�� assign leds_out = counter;�� // note that this will map all 7 bits

�� always @(posedge clk or posedge rst)

�� if( rst) counter <= 127;�� // default notation is in decimal

�� else counter <= next_count;

�� // We use a seperate section to compute what value the counter should take on, based on the inputs.

�� always @(counter or cntdwn or cntup) begin

�� next_count = counter;

�� if( cntdwn&~cntup)� next_count = counter - 1;

�� if(~cntdwn&cntup)� next_count = counter + 1;

��

�� end

�� /*�

�� But, there is a slight complication.

�� We can't just use the cntdown signal directly from the push-buttons.�

�� The resoning will be covered more in the lectures.�

�� We need to feed it through a flip-flop first.

�� */

�� always @(posedge clk or posedge rst)

�� if( rst) cntdwn <= 0;

�� else cntdwn <= cntdwn_from_pushbutton;

�� always @(posedge clk or posedge rst)

�� if( rst) cntup <= 0;

�� else cntup <= cntup_from_pushbutton;

endmodule

Constrain File updncounter.ucf

#PINLOCK_BEGIN

#Mon Nov 29 13:29:45 2004

#PINLOCK_END

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments

NET "clk" LOC = "D9";

NET "leds_out<0>" LOC = "K12";

NET "leds_out<1>" LOC = "P14";

NET "leds_out<2>" LOC = "L12";

NET "leds_out<3>" LOC = "N14";

NET "leds_out<4>" LOC = "P13";

NET "leds_out<5>" LOC = "N12";

NET "leds_out<6>" LOC = "P12";

NET "pbl" LOC = "L13";

NET "pbr" LOC = "M13";

NET "rst" LOC = "L14";

NET "status<0>" LOC = "R16";

NET "status<1>" LOC = "P15";

NET "status<2>" LOC = "N15";

NET "status<3>" LOC = "N16";

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Test Bench File updncounter_tb.v

� module updncounter_tb;��

�� reg pbl;�� // inputs to your circuit are declared as registers

�� reg rst;

�� reg pbr;

�� reg clk;

�� wire [6:0] leds_out;�� // outputs from your circuit are declared as wires

�� always #20� clk <= ~clk;�� // toggles the clock every 20 time units

�� initial begin�� // All initial statements start from the same time, t=0.

�� clk =0; rst=0; pbl=0; pbr=0;�� // initialize all inputs to something

��

�� @( posedge clk);�� // wait for the first clock edge

�� #5; rst=1;�� // turn on the reset

�� @( posedge clk);�� // wait for another clock edge

�� #5; rst=0;�� // turn off the reset

�� // it should be holding in reset��

�� repeat(10) @(posedge clk);

�� #5;

�� pbr =1;

�� // Now, the counter should be merrily counting up

�� // we will wait until is reaches 69 and then switch directions

�� wait( leds_out==69);

�� $display("%t - TESTBENCH: The counter has reached 69", $time);

�� @( posedge clk);

�� #5; pbl = 1; pbr= 0;

�� $display("%t - TESTBENCH: Switching Directions", $time);

�� wait( leds_out==0);

�� $display("%t - TESTBENCH: The counter has reached 0 - Finishing.", $time);

�� $finish;

�� end ��

�� // every time the clock falls, print out the value of the leds

�� always @(posedge clk) $display("%t - CLKSAMPLE: Leds sampled to be %d", $time, leds_out);

�� // set up statements to inform you when inputs change

�� always @(rst)�� $display("%t - DATAMONITOR: rst signal changed to %b", $time, rst);

�� // and finally instantiate the device under test (DUT)

�� updncounter updncounter_instance(.clk(clk), .rst(rst), .pbl(pbl), .pbr(pbr), .leds_out(leds_out));

� endmodule

ISE design Flow

Xilinx Spartan 3 Family

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